ACADEMIC YEAR | U.G | P.G | ||||
ELECTIVE NO | LEVEL | ELECTIVE COURSE OFFERED | ELECTIVE NO | LEVEL | ELECTIVE COURSE OFFERED | |
2020-21 | OPEN ELECTIVE | III/II | OOPS THROUGH JAVA | I | I/I | VLSI TECHNOLOGY |
I | IV/I | ELECTRONIC SWITCHING SYSTEMS | II | I/I | PHOTONICS | |
II | IV/I | EMBEDDED SYSTEMS | III | I/II | DESIGN FOR TESTABILITY | |
III | IV/II | WIRELESS SENSOR NETWORKS | IV | I/II | LOW POWER VLSI DESIGN | |
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| V | II/III | DIGITAL SYSTEM DESIGN & VERIFICATION | |
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| OPEN ELECTIVE | II/III | WASTE TO ENERGY | |
2019-20 | OPEN ELECTIVE | III/II | OOPS THROUGH JAVA | I | I/I | VLSI TECHNOLOGY |
I | IV/I | ELECTRONIC SWITCHING SYSTEMS | II | I/I | PHOTONICS | |
II | IV/I | EMBEDDED SYSTEMS | III | I/II | DESIGN FOR TESTABILITY | |
III | IV/II | WIRELESS SENSOR NETWORKS | IV | I/II | LOW POWER VLSI DESIGN | |
2018-19 | OPEN ELECTIVE | III/II | BIO MEDICAL ENGINEERING | I | I/I | DIGITAL DESIGN USING HDL |
I | IV/I | RADAR SYSTEMS | II | I/I | CPLD AND FPGA ARCHITECTURES AND APPLICATIONS | |
II | IV/I | OPTICAL COMMUNICATIONS | III | I/II | DS P PROCESSORS AND ARCHITECTURES | |
III | IV/II | SATELLITE COMMUNICATION | IV | I/II | SEMICONDUCTOR MEMORY DESIGN AND TESTING | |
IV | IV/II | WIRELESS SENSOR NETWORKS | – | – |
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2017-18 | OPEN ELECTIVE | III/II | BIO MEDICAL ENGINEERING | I | I/I | DIGITAL DESIGN USING HDL |
I | IV/I | RADAR SYSTEMS | II | I/I | CPLD AND FPGA ARCHITECTURES AND APPLICATIONS | |
II | IV/I | OPTICAL COMMUNICATIONS | III | I/II | DS P PROCESSORS AND ARCHITECTURES | |
III | IV/II | SATELLITE COMMUNICATION | IV | I/II | SEMICONDUCTOR MEMORY DESIGN AND TESTING | |
IV | IV/II | WIRELESS SENSOR NETWORKS |
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2016-17 | OPEN ELECTIVE | III/II | BIO MEDICAL ENGINEERING | I | I/I | DIGITAL DESIGN USING HDL |
I | IV/I | RADAR SYSTEMS | II | I/I | CPLD AND FPGA ARCHITECTURES AND APPLICATIONS | |
II | IV/I | OPTICAL COMMUNICATIONS | III | I/II | DS P PROCESSORS AND ARCHITECTURES | |
III | IV/II | SATELLITE COMMUNICATION | IV | I/II | SEMICONDUCTOR MEMORY DESIGN AND TESTING | |
IV | IV/II | WIRELESS SENSOR NETWORKS |
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2015-16 | OPEN ELECTIVE | IV/I | BIO MEDICAL ENGINEERING | I | I/I | DIGITAL SYSTEM DESIGN |
OPEN ELECTIVE (R13) | III/II | BIO MEDICAL ENGINEERING | II | I/I | DIGITAL DESIGN USING HDL | |
I | IV/I | TELECOMMUNICATION SWITCHING SYSTEM | III | I/II | DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES | |
II | IV/II | SATELLITE COMMUNICATION | IV | I/II | SEMICONDUCTOR MEMORY DESIGN AND TESTING | |
III | IV/II | WIRELESS SENSOR NETWORKS |
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IV | IV/II | REAL TIME OPERATING SYSTEMS |
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2014-15 | OPEN ELECTIVE | IV/I | BIO MEDICAL ENGINEERING | I | I/I | DIGITAL SYSTEM DESIGN |
I | IV/I | TELECOMMUNICATION SWITCHING SYSTEM | II | I/I | DIGITAL DESIGN USING HDL | |
II | IV/II | SATELLITE COMMUNICATION | III | I/II | DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES | |
III | IV/II | WIRELESS SENSOR NETWORKS | IV | I/II | SEMICONDUCTOR MEMORY DESIGN AND TESTING | |
IV | IV/II | REAL TIME OPERATING SYSTEMS |
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2013-14 | OPEN ELECTIVE | IV/I | BIO MEDICAL ENGINEERING | I | I/I | DIGITAL SYSTEM DESIGN |
I | IV/I | TELECOMMUNICATION SWITCHING SYSTEM | II | I/I | DIGITAL DESIGN USING HDL | |
II | IV/II | SATELLITE COMMUNICATION | III | I/II | DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES | |
III | IV/II | WIRELESS SENSOR NETWORKS | IV | I/II | SEMICONDUCTOR MEMORY DESIGN AND TESTING | |
IV | IV/II | REAL TIME OPERATING SYSTEMS |
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2012-13 | I | IV/I | MICRO CONTROLLERS AND APPLICATIONS | I | I/I | VHDL MODELING OF DIGITAL SYSTEMS |
II | IV/I | DIGITAL IMAGE PROCESSING | II | I/I | EMBEDDED SYSTEM DESIGN | |
III | IV/II | EMBEDDED AND REAL TIME SYSTEMS | III | I/II | EMBEDDED AND REAL TIME SYSTEMS | |
IV | IV/II | DSP PROCESSORS AND ARCHITECTURES | IV | I/II | CPLD AND FPGA ARCHITECTURE AND APPLICATIONS | |
2011-12 | I | IV/I | MICRO CONTROLLERS AND APPLICATIONS |
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II | IV/I | DIGITAL IMAGE PROCESSING |
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III | IV/II | EMBEDDED AND REAL TIME SYSTEMS |
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IV | IV/II | DSP PROCESSORS AND ARCHITECTURES |
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2010-11 | I | IV/I | TELEVISION ENGINEERING |
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II | IV/I | DIGITAL IMAGE PROCESSING |
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III | IV/II | EMBEDDED AND REAL TIME SYSTEMS |
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IV | IV/II | DSP PROCESSORS AND ARCHITECTURES |
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2009-10 | I | IV/I | TELEVISION ENGINEERING |
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II | IV/I | DIGITAL IMAGE PROCESSING |
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III | IV/II | EMBEDDED AND REAL TIME SYSTEMS |
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IV | IV/II | DSP PROCESSORS AND ARCHITECTURES |
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2008-09 | I | IV/I | TELEVISION ENGINEERING |
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II | IV/I | DIGITAL IMAGE PROCESSING |
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III | IV/II | EMBEDDED AND REAL TIME SYSTEMS |
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IV | IV/II | DSP PROCESSORS AND ARCHITECTURES |
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2007-08 | I | IV/I | SATELLITE COMMUNICATION |
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II | IV/I | DIGITAL IMAGE PROCESSING |
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III | IV/II | CELLULAR & MOBILE COMMUNICATION |
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IV | IV/II | RADAR ENGINEERING |
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2006-07 | I | IV/I | SATELLITE COMMUNICATION |
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II | IV/I | DIGITAL IMAGE PROCESSING |
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III | IV/II | CELLULAR & MOBILE COMMUNICATION |
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IV | IV/II | RADAR ENGINEERING |
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2005-06 | I | IV/I | SATELLITE COMMUNICATION |
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II | IV/I | DIGITAL IMAGE PROCESSING |
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III | IV/II | CELLULAR & MOBILE COMMUNICATION |
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IV | IV/II | RADAR ENGINEERING |
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